FDC37C93XAPM View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37C93XAPM

Plug and Play Compatible Ultra I/O™ Controller with Soft Power Management

SMSC -> Microchip 

FIFO

MODE

ONLY

BIT

3

0

0

0

1

0

0

INTERRUPT

IDENTIFICATION

REGISTER

BIT BIT BIT

2

1

0

0

0

1

1

1

0

1

0

0

1

0

0

0

1

0

0

0

0

Table 32 - Interrupt Control Table

INTERRUPT SET AND RESET FUNCTIONS

PRIORITY INTERRUPT

LEVEL

TYPE

INTERRUPT

SOURCE

INTERRUPT

RESET CONTROL

-

None

None

-

Highest

Receiver Line

Status

Overrun Error,

Parity Error,

Framing Error or

Break Interrupt

Reading the Line

Status Register

Second

Received Data Receiver Data

Available

Available

Read Receiver

Buffer or the FIFO

drops below the

trigger level.

Second

Character

Timeout

Indication

No Characters

Have Been

Removed From

or Input to the

RCVR FIFO

during the last 4

Char times and

there is at least 1

char in it during

this time

Reading the

Receiver Buffer

Register

Third

Transmitter

Transmitter

Holding Register Holding Register

Empty

Empty

Reading the IIR

Register (if Source

of Interrupt) or

Writing the

Transmitter Holding

Register

Fourth

MODEM Status

Clear to Send or

Data Set Ready

or Ring Indicator

or Data Carrier

Detect

Reading the

MODEM Status

Register

73

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