CAM35C44 View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
Manufacturer
CAM35C44 Datasheet PDF : 50 Pages
| |||
CR00 - IRQ Control
The IRQ Control register CR00 determines the
IRQ pin polarity and enables the configuration
register locking feature.
CR00 can only be accessed in the
configuration state and only after the CSR has
been initialized to 00H. The default value of this
register after power up is 00H (TABLE 14).
Bits[7:3, 1] in the IRQ Control register are
RESERVED.
TABLE 14 - IRQ CONTROL REGISTER
D7 D6 D5 D4 D3
D2
D1
D0
DEFAULT
CR00 R/W
RESERVED
LOCK
RES IRQ_LEV
0x00
IRQ_LEV, Bit 0
The IRQ_LEV bit D0 determines the active state
of the IRQ output pin (TABLE 1). If IRQ_LEV is
“0” (default), the IRQ pin is active low. If
IRQ_LEV is “1”, the IRQ pin is active high.
Note: once the LOCK bit is set to “1” the
configuration registers are permanently locked.
The LOCK bit can only be reset to “0” by a hard-
reset or a power-on-reset; i.e., the configuration
registers cannot be changed until either a hard-
reset or power-on-reset occur.
LOCK, Bit 2
CR01 - DMA Control
The LOCK bit D2 selects configuration register
locking. “Locked” means configuration registers
can be read but cannot be written, except for the
IRCC Legacy Controls like the IR HALF
DUPLEX TIME-OUT that can be written through
the SCE Registers and appear in the chip-level
configuration registers regardless of the state of
the LOCK bit.
If LOCK is “0” (default), the configuration
registers are unlocked. If LOCK is “1”, the
configuration registers are locked.
The DMA Control register CR01 determines the
DRQ and DACK pin polarity (TABLE 1).
CR01 can only be accessed in the configuration
state and only after the CSR has been initialized
to 01H. The default value of this register after
power up is 00H (TABLE 15).
Bits[7:2] in the DMA Control register are
RESERVED.
TABLE 15 - DMA CONTROL REGISTER (CR01)
D7 D6 D5 D4 D3 D2
D1
D0
CR01 R/W
RESERVED
DAC_LEV DREQ_LEV
DEFAULT
0x00
22
Share Link: 