ADP3208CJCPZ-RL View Datasheet(PDF) - ON Semiconductor

Part Name

Description

Manufacturer

ADP3208CJCPZ-RL

7-Bit, Programmable, Dual-Phase, Mobile, CPU, Synchronous Buck Controller

ON Semiconductor 

ADP3208C

In VCC UVLO or in shutdown, a small MOSFET turns on

connecting the CSREF to GND. The MOSFET on the CSREF

pin has a resistance of approximately 100Ω. When VCC ramps

above the upper UVLO threshold and EN is asserted high, the

ADP3208C enables internal bias and starts a reset cycle that

lasts about 50 μs to 60 μs. Next, when initial reset is over, the

chip detects the number of phases set by the user, and gives a go

signal to start soft start. The ADP3208C reads the VID codes

provided by the CPU on VID0 to VID6 input pins after

CLKEN# is asserted low.The PWRGD signal is asserted after a

tCPU_PWRGD delay of about 9 ms, as specified by IMVP-6+. The

power-good delay is programmed internally.

Figure 25. Power-Up Sequence of ADP3208C

If EN is taken low or VCC drops below the VCC UVLO

threshold, both the SS capacitor and the PGDELAY capacitor

are reset to ground to prepare the chip for a subsequent soft

start cycle.

SOFT TRANSIENT

When a VID input changes, the ADP3208C detects the change but

ignores new code for a minimum of 400 ns. This delay is required to

prevent the device from reacting to digital signal skew while the 7-

bit VID input code is in transition. Additionally, the VID change

triggers a PWRGD masking timer to prevent a PWRGD failure.

Each VID change resets and retriggers the internal PWRGD

masking timer.

The ADP3208C provides a soft transient function to reduce inrush

current during VID transitions. Reducing the inrush current helps

decrease the acoustic noise generated by the MLCC input capacitors

and inductors.

The soft transient feature is implemented internally. When a new

VID code is detected, the ADP3208C steps sequentially through

each VID voltage to the final VID voltage. There is a PWRGD

masking time of 100μs after the last VID code is changed internally.

Table 5 lists the soft transient slew rate.

Table 5. Soft Transient Slew Rate

VID Transient

DPRSLP

Entrance to Deeper Sleep HIGH

Fast Exit from Deeper Sleep LOW

Slow Exit from Deeper Sleep HIGH

Transient from VBOOT to VID DNC1

Slew Rate

−3.125mV/μs

+12.5mV/μs

+3.125mV/μs

±3.125mV/μs

CURRENT LIMIT

The ADP3208C compares the differential output of a current-

sense amplifier to a programmable current-limit setpoint to

provide current-limiting function. The current limit set point is

set with a resistor connected from ILIM pin to CSCOMP pin.

This is the Rlim resistor. During normal operation, the voltage

on the ILIM pin is equal to the CSREF pin. The voltage across

Rlim is equal to the voltage across the current sense amplifier

(from CSREF pin to CSCOMP pin). This voltage is

proportional to output current. The current through Rlim is

proportional to the output inductor current. The current

through Rlim is compared with an internal reference current.

When the Rlim current goes above the internal reference current,

the ADP3208C goes into current limit. The current limit circuit

is shown in figure 28.

Figure28. Current Limit Circuit

During start-up when the output voltage is below 200 mV, a

secondary current limit is activated. This is necessary because

the voltage swing on CSCOMP cannot extend below ground.

The secondary current-limit circuit clamps the internal COMP

voltage and sets the internal compensation ramp termination

voltage at 1.5 V level. The clamp actually limits voltage drop

across the low side MOSFETs through the current balance

circuitry.

An inherent per phase current limit protects individual phases

in case one or more phases stop functioning because of a faulty

component. This limit is based on the maximum normal-mode

COMP voltage.

Rev. 1 | Page 24 of 41 | www.onsemi.com

Share Link: