ATXMEGA32A4-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
ATXMEGA32A4-CU Datasheet PDF : 107 Pages
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Figure 25-1. ADC overview
Channel A MUX selection
Channel B MUX selection
Channel C MUX selection
Channel D MUX selection
Configuration
Reference selection
ADC
1-64 X
Event
Trigger
XMEGA A4
Channel A
Register
Channel B
Register
Channel C
Register
Channel D
Register
Each ADC has four MUX selection registers with a corresponding result register. This means
that four channels can be sampled within 1.5 µs without any intervention by the application other
than starting the conversion. The results will be available in the result registers.
The ADC may be configured for 8- or 12-bit resolution, reducing the minimum conversion time
(propagation delay) from 3.5 µs for 12-bit to 2.5 µs for 8-bit resolution.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This
eases calculation when the result is represented as a signed integer (signed 16-bit number).
PORTA has one ADC. Notation of this peripheral is ADCA.
42
8069O–AVR–08/10
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