C8051F020 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F020

8K ISP FLASH MCU Family

Silicon Laboratories 

C8051F020/1/2/3

12.3.3. Interrupt Priorities

Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority inter-

rupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted. Each

interrupt has an associated interrupt priority bit in an SFR (IP-EIP2) used to configure its priority level. Low priority

is the default. If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If

both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in Table 12.4.

12.3.4. Interrupt Latency

Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled

and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5 system clock cycles:

1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR. If an interrupt is pending

when a RETI is executed, a single instruction is executed before an LCALL is made to service the pending interrupt.

Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the

new interrupt is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as the

next instruction. In this case, the response time is 18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock

cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL

to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be

serviced until the current ISR completes, including the RETI and following instruction.

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Rev. 1.4

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