C8051F020 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F020

8K ISP FLASH MCU Family

Silicon Laboratories 

C8051F020/1/2/3

Figure 17.7. XBR0: Port I/O Crossbar Register 0

R/W

CP0E

Bit7

R/W

ECI0E

Bit6

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

PCA0ME

UART0EN SPI0EN SMB0EN 00000000

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0 SFR Address:

0xE1

Bit7:

Bit6:

Bits5-3:

Bit2:

Bit1:

Bit0:

CP0E: Comparator 0 Output Enable Bit.

0: CP0 unavailable at Port pin.

1: CP0 routed to Port pin.

ECI0E: PCA0 External Counter Input Enable Bit.

0: PCA0 External Counter Input unavailable at Port pin.

1: PCA0 External Counter Input (ECI0) routed to Port pin.

PCA0ME: PCA0 Module I/O Enable Bits.

000: All PCA0 I/O unavailable at Port pins.

001: CEX0 routed to Port pin.

010: CEX0, CEX1 routed to 2 Port pins.

011: CEX0, CEX1, and CEX2 routed to 3 Port pins.

100: CEX0, CEX1, CEX2, and CEX3 routed to 4 Port pins.

101: CEX0, CEX1, CEX2, CEX3, and CEX4 routed to 5 Port pins.

110: RESERVED

111: RESERVED

UART0EN: UART0 I/O Enable Bit.

0: UART0 I/O unavailable at Port pins.

1: UART0 TX routed to P0.0, and RX routed to P0.1.

SPI0EN: SPI0 Bus I/O Enable Bit.

0: SPI0 I/O unavailable at Port pins.

1: SPI0 SCK, MISO, MOSI, and NSS routed to 4 Port pins.

SMB0EN: SMBus0 Bus I/O Enable Bit.

0: SMBus0 I/O unavailable at Port pins.

1: SMBus0 SDA and SCL routed to 2 Port pins.

170

Rev. 1.4

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