C8051F020 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F020

8K ISP FLASH MCU Family

Silicon Laboratories 

C8051F020/1/2/3

21.3. Frame and Transmission Error Detection

Frame error detection is available in the following modes when the SSTAT1 bit in register PCON is set to logic 1.

Note: The SSTAT1 bit must be logic 1 to access any of the status bits (FE1, RXOVR1, and TXCOL1). To access the

UART1 Mode Select bits (SM01, SM11, and SM21), the SSTAT1 bit must be logic 0.

All Modes:

The Transmit Collision bit (TXCOL1 bit in register SCON1) reads ‘1’ if user software writes data to the SBUF1 reg-

ister while a transmit is in progress. Note that the TXCOL1 bit also functions as the SM21 bit when the SSTAT1 bit in

register PCON is logic 0.

Modes 1, 2, and 3:

The Receive Overrun bit (RXOVR1 in register SCON1) reads ‘1’ if a new data byte is latched into the receive buffer

before software has read the previous byte. Note that the RXOVR1 bit also functions as the SM11 bit when the

SSTAT1 bit in register PCON is logic 0.

The Frame Error bit (FE1 in register SCON1) reads ‘1’ if an invalid (low) STOP bit is detected. Note that the FE1 bit

also functions as the SM01 bit when the SSTAT1 bit in register PCON is logic 0.

Rev. 1.4

221

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