C8051F020 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F020

8K ISP FLASH MCU Family

Silicon Laboratories 

C8051F020/1/2/3

Bit

118, 120, 122, 124,

126, 128, 130, 132

119, 121, 123, 125,

127, 129, 131, 133

Table 24.1. Boundary Data Register Bit Definitions

Action Target

Capture P7.n output enable from MCU

Update P7.n output enable to pin

Capture P7.n input from pin

Update P7.n output to pin

24.1.1. EXTEST Instruction

The EXTEST instruction is accessed via the IR. The Boundary DR provides control and observability of all the

device pins as well as the Weak Pullup feature. All inputs to on-chip logic are set to logic 1.

24.1.2. SAMPLE Instruction

The SAMPLE instruction is accessed via the IR. The Boundary DR provides observability and presetting of the scan-

path latches.

24.1.3. BYPASS Instruction

The BYPASS instruction is accessed via the IR. It provides access to the standard JTAG Bypass data register.

24.1.4. IDCODE Instruction

The IDCODE instruction is accessed via the IR. It provides access to the 32-bit Device ID register.

Figure 24.2. DEVICEID: JTAG Device ID Register

Version

Part Number

Bit31

Bit28 Bit27

Bit12 Bit11

Manufacturer ID

Reset Value

1

0xn0003243

Bit1

Bit0

Version = 0000b

Part Number = 0000 0000 0000 0011b (C8051F020/1/2/3)

Manufacturer ID = 0010 0100 001b (Silicon Labs)

Rev. 1.4

267

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