GAL16LV8C-10LJ View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

GAL16LV8C-10LJ

Low Voltage E2CMOS PLD eneric Array Logic™

Lattice Semiconductor 

Specifications GAL16LV8

Complex Mode

In the Complex mode, macrocells are configured as output only or

I/O functions.

signs requiring eight I/Os can be implemented in the Registered

mode.

Architecture configurations available in this mode are similar to the All macrocells have seven product terms per output. One product

common 16L8 and 16P8 devices with programmable polarity in term is used for programmable output enable control. Pins 1 and

each macrocell.

11 are always available as data inputs into the AND array.

Up to six I/Os are possible in this mode. Dedicated inputs or outputs The JEDEC fuse numbers including the UES fuses and PTD fuses

can be implemented as subsets of the I/O function. The two outer are shown on the logic diagram on the following page.

most macrocells (pins 12 & 19) do not have input capability. De-

XOR

Combinatorial I/O Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1.

- Pin 13 through Pin 18 are configured to this function.

XOR

Combinatorial Output Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1.

- Pin 12 and Pin 19 are configured to this function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

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