LH28F160S5T-L80 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
Manufacturer
LH28F160S5T-L80
Sharp Electronics
LH28F160S5T-L80 Datasheet PDF : 55 Pages
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Reliable multi byte writes can only occur when VCC
= VCC1/2 and VPP = VPPH1. In the absence of this
high voltage, memory contents are protected
against multi word/byte writes. If multi word/byte
write is attempted while VPP ≤ VPPLK, status
register bits SR.3 and SR.4 will be set to "1".
Successful multi word/byte write requires that the
corresponding block lock-bit be cleared or, if set,
that WP# = VIH. If multi byte write is attempted
when the corresponding block lock-bit is set and
WP# = VIL, SR.1 and SR.4 will be set to "1".
4.10 Block Erase Suspend Command
The Block Erase Suspend command allows block
erase interruption to read or (multi) word/byte write
data in another block of memory. Once the block
erase process starts, writing the Block Erase
Suspend command requests that the WSM
suspend the block erase sequence at a
predetermined point in the algorithm. The device
outputs status register data when read after the
Block Erase Suspend command is written. Polling
status register bits SR.7 and SR.6 can determine
when the block erase operation has been
suspended (both will be set to "1"). STS will also
transition to High Z. Specification tWHRH2 defines
the block erase suspend latency.
At this point, a Read Array command can be
written to read data from blocks other than that
which is suspended. A (Multi) Word/Byte Write
command sequence can also be issued during
erase suspend to program data in other blocks.
Using the (Multi) Word/Byte Write Suspend
command (see Section 4.11), a (multi) word/byte
write operation can also be suspended. During a
(multi) word/byte write operation with block erase
suspended, status register bit SR.7 will return to "0"
and the STS (if set to RY/BY#) output will transition
to VOL. However, SR.6 will remain "1" to indicate
block erase suspend status.
The only other valid commands while block erase is
LH28F160S5-L/S5H-L
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status register
bits SR.6 and SR.7 will automatically clear and STS
will return to VOL. After the Erase Resume
command is written, the device automatically
outputs status register data when read (see Fig. 8).
VPP must remain at VPPH1 (the same VPP level
used for block erase) while block erase is
suspended. RP# must also remain at VIH. Block
erase cannot resume until (multi) word/byte write
operations initiated during block erase suspend
have completed.
4.11 (Multi) Word/Byte Write Suspend
Command
The (Multi) Word/Byte Write Suspend command
allows (multi) word/byte write interruption to read
data in other flash memory locations. Once the
(multi) word/byte write process starts, writing the
(Multi) Word/Byte Write Suspend command
requests that the WSM suspend the (multi)
word/byte write sequence at a predetermined point
in the algorithm. The device continues to output
status register data when read after the (Multi)
Word/Byte Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can
determine when the (multi) word/byte write
operation has been suspended (both will be set to
"1"). STS will also transition to High Z. Specification
tWHRH1 defines the (multi) word/byte write suspend
latency.
At this point, a Read Array command can be
written to read data from locations other than that
which is suspended. The only other valid
commands while (multi) word/byte write is
suspended are Read Status Register and (Multi)
Word/Byte Write Resume. After (Multi) Word/Byte
Write Resume command is written to the flash
memory, the WSM will continue the (multi)
word/byte write process. Status register bits SR.2
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