LH28F160S5T-L80 View Datasheet(PDF) - Sharp Electronics

Part Name

Description

Manufacturer

LH28F160S5T-L80

16 M-bit (2 MB x 8/1 MB x 16) Smart 5 Flash Memories (Fast Programming)

Sharp Electronics 

LH28F160S5-L/S5H-L

protected against alteration. A successful clear

block lock-bits operation requires WP# = VIH. If it is

attempted with WP# = VIL, SR.1 and SR.5 will be

set to "1" and the operation will fail. Clear block

lock-bits operation with VIH < RP# produce spurious

results and should not be attempted.

If a clear block lock-bits operation is aborted due to

VPP or VCC transition out of valid range or RP#

active transition, block lock-bit values are left in an

undetermined state. A repeat of clear block lock-bits

is required to initialize block lock-bit contents to

known values.

4.14 STS Configuration Command

The Status (STS) pin can be configured to different

states using the STS Configuration command.

Once the STS pin has been configured, it remains

in that configuration until another configuration

command is issued, the device is powered down or

RP# is set to VIL. Upon initial device power-up and

after exit from deep power-down mode, the STS

pin defaults to RY/BY# operation where STS low

indicates that the WSM is busy. STS High Z

indicates that the WSM is ready for a new

operation.

To reconfigure the STS pin to other modes, the

STS Configuration is issued followed by the

appropriate configuration code. The three alternate

configurations are all pulse mode for use as a

system interrupt. The STS Configuration command

functions independently of the VPP voltage and

RP# must be VIH.

Table 11 STS Configuration Coding Description

CONFIGURATION

BITS

EFFECTS

Set STS pin to default level mode

(RY/BY#). RY/BY# in the default

00H

level-mode of operation will indicate

WSM status condition.

Set STS pin to pulsed output signal

for specific erase operation. In this

01H

mode, STS provides low pulse at the

completion of Block Erase, Full Chip

Erase and Clear Block Lock-Bits

operations.

Set STS pin to pulsed output signal

for a specific write operation. In this

02H

mode, STS provides low pulse at the

completion of (Multi) Byte Write and

Set Block Lock-Bit operation.

Set STS pin to pulsed output signal

for specific write and erase operation.

03H

STS provides low pulse at the

completion of Block Erase, Full Chip

Erase, (Multi) Word/Byte Write and

Block Lock-Bit Configuration operations.

Table 12 Write Protection Alternatives

OPERATION

BLOCK WP#

LOCK-BIT

EFFECT

Block Erase or

0

VIL or VIH Block Erase and (Multi) Word/Byte Write Enabled

(Multi) Word/Byte

Write

1

VIL Block is Locked. Block Erase and (Multi) Word/Byte Write Disabled

VIH Block Lock-Bit Override. Block Erase and (Multi) Word/Byte Write Enabled

Full Chip Erase

0, 1

VIL All unlocked blocks are erased, locked blocks are not erased

X

VIH All blocks are erased

Set Block Lock-Bit

X

VIL Set Block Lock-Bit Disabled

VIH Set Block Lock-Bit Enabled

Clear Block Lock-Bits X

VIL Clear Block Lock-Bits Disabled

VIH Clear Block Lock-Bits Enabled

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