MAX1225ETC-T(2009) View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX1225ETC-T
(Rev.:2009)
(Rev.:2009)
Maxim Integrated
MAX1225ETC-T Datasheet PDF : 18 Pages
| |||
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
Typical Operating Characteristics (continued)
(VDD = +3V, VL = VDD, VREF = 2.048V, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA = -40°C to +85°C, unless otherwise noted. Typical
values are measured at TA = +25°C)
VDD SUPPLY CURRENT
vs. CONVERSION RATE
9
VL SUPPLY CURRENT vs. TEMPERATURE
0.5
250
VL SUPPLY CURRENT
vs. CONVERSION RATE
6
3
0
0 250 500 750 1000 1250 1500
fSAMPLE (kHz)
0.4
CONVERSION, VL = 3V
0.3
0.2
CONVERSION, VL = 1.8V
0.1
0
-40 -15
10
35
60
85
TEMPERATURE (°C)
200
150
VL = 3V
100
50
0
0
VL = 1.8V
250 500 750 100 1250 1500
fSAMPLE (kHz)
PIN
1
2
3
4
5, 11
6
7
8
9
10
12
—
NAME
AIN-
REF
RGND
VDD
N.C.
GND
VL
DOUT
CNVST
SCLK
AIN+
EP
Pin Description
FUNCTION
Negative Analog Input
External Reference Voltage Input. VREF sets the analog input range. Bypass REF with a 0.01µF
capacitor and a 4.7µF capacitor to RGND.
Reference Ground. Connect RGND to GND.
Positive Analog Supply Voltage (+2.7V to +3.6V). Bypass VDD with a 0.01µF capacitor and a 10µF
capacitor to GND.
No Connection
Ground. GND is internally connected to EP.
Positive Logic Supply Voltage (1.8V to VDD). Bypass VL with a 0.01µF capacitor and a 10µF capacitor
to GND.
Serial Data Output. Data is clocked out on the rising edge of SCLK.
Convert Start. Forcing CNVST high prepares the part for a conversion. Conversion begins on the
falling edge of CNVST. The sampling instant is defined by the falling edge of CNVST.
Serial Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed.
Positive Analog Input
Exposed Paddle. EP is internally connected to GND.
8 _______________________________________________________________________________________
Share Link: 