MCP2510
FIGURE 6-1:
ERROR MODES STATE DIAGRAM
RESET
REC > 127 or
TEC > 127
Error-Passive
Error-Active
REC < 127 or
TEC < 127
128 occurrences of
11 consecutive
“recessive” bits
TEC > 255
Bus-Off
REGISTER 6-1:
TEC - TRANSMITTER ERROR COUNTER (ADDRESS: 1Ch)
R-0
TEC7
bit 7
R-0
TEC6
R-0
TEC5
R-0
TEC4
R-0
TEC3
R-0
TEC2
R-0
TEC1
R-0
TEC0
bit 0
bit 7-0
TEC<7:0>: Transmit Error Count
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
REGISTER 6-2:
REC - RECEIVER ERROR COUNTER (ADDRESS: 1Dh)
R-0
REC7
bit 7
R-0
REC6
R-0
REC5
R-0
REC4
R-0
REC3
R-0
REC2
R-0
REC1
R-0
REC0
bit 0
bit 7-0
REC<7:0>: Receive Error Count
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
DS21291F-page 42
© 2007 Microchip Technology Inc.