PIC17LC752-08/JWQTP View Datasheet(PDF) - Microchip Technology

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Description

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PIC17LC752-08/JWQTP

High-Performance 8-Bit CMOS EPROM Microcontrollers

Microchip Technology 

15.3 Connection Considerations for I2C

Bus

For standard-mode I2C bus devices, the values of

resistors Rp Rs in Figure 15-45 depends on the follow-

ing parameters

• Supply voltage

• Bus capacitance

• Number of connected devices (input current +

leakage current).

The supply voltage limits the minimum value of resistor

Rp due to the specified minimum sink current of 3 mA

at VOL max = 0.4V for the specified output stages. For

example, with a supply voltage of VDD = 5V+10% and

VOL max = 0.4V at 3 mA, Rp min = (5.5-0.4)/0.003 =

1.7 kΩ. VDD as a function of Rp is shown in

Figure 15-45. The desired noise margin of 0.1VDD for

the low level, limits the maximum value of Rs. Series

resistors are optional.

PIC17C75X

The bus capacitance is the total capacitance of wire,

connections, and pins. This capacitance limits the max-

imum value of Rp due to the specified rise time

(Figure 15-45).

The SMP bit is the slew rate control enabled bit. This bit

is in the SSPSTAT register, and controls the slew rate

of the I/O pins when in I2C mode (master or slave).

This control ensures that the rise and fall times of the

SCL and SDA pins will meet the minimum require-

ments as specified in the I2C specification for 400 kHz

operation.

FIGURE 15-45: SAMPLE DEVICE CONFIGURATION FOR I2C BUS

VDD + 10%

Rp

Rp

DEVICE

Rs Rs

SDA

SCL

NOTE: I2C devices with input levels related to VDD must have one common supply

line to which the pull up resistor is also connected.

Cb=10 - 400 pF

© 1997 Microchip Technology Inc.

Preliminary

DS30264A-page 165

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