PIC17C752-08LQTP View Datasheet(PDF) - Microchip Technology
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PIC17C752-08LQTP Datasheet PDF : 320 Pages
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7.1.2 EXTERNAL MEMORY INTERFACE
When either microprocessor or extended microcontrol-
ler mode is selected, PORTC, PORTD and PORTE are
configured as the system bus. PORTC and PORTD are
the multiplexed address/data bus and PORTE<2:0> is
for the control signals. External components are
needed to demultiplex the address and data. This can
be done as shown in Figure 7-4. The waveforms of
address and data are shown in Figure 7-3. For com-
plete timings, please refer to the electrical specification
section.
FIGURE 7-3:
EXTERNAL PROGRAM
MEMORY ACCESS
WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
AD
<15:0>
ALE
OE
WR
Address out Data in
'1'
Read cycle
Address out Data out
Write cycle
The system bus requires that there is no bus conflict
(minimal leakage), so the output value (address) will be
capacitively held at the desired value.
As the speed of the processor increases, external
EPROM memory with faster access time must be used.
Table 7-2 lists external memory speed requirements for
a given PIC17C75X device frequency.
PIC17C75X
In extended microcontroller mode, when the device is
executing out of internal memory, the control signals
will continue to be active. That is, they indicate the
action that is occurring in the internal memory. The
external memory access is ignored.
This following selection is for use with Microchip
EPROMs. For interfacing to other manufacturers mem-
ory, please refer to the electrical specifications of the
desired PIC17C75X device, as well as the desired
memory device to ensure compatibility.
TABLE 7-2: EPROM MEMORY ACCESS
TIME ORDERING SUFFIX
PIC17C75X Instruction
Oscillator Cycle
Frequency Time (TCY)
EPROM Suffix
PIC17C752
PIC17C756
8 MHz
500 ns
-25
16 MHz
250 ns
-15
20 MHz
200 ns
-10
25 MHz
160 ns
-70
33 MHz
121 ns
(1)
Note 1: The access times for this requires the use of
fast SRAMs.
FIGURE 7-4: TYPICAL EXTERNAL PROGRAM MEMORY CONNECTION DIAGRAM
AD15-AD0
AD7-AD0
PIC17CXXX
A15-A0
373
AD15-AD8
373
ALE
I/O(1)
OE
WR
Note 1: Use of I/O pins is only required for paged memory.
2: This signal is unused for ROM and EPROM devices.
138(1)
Memory
(MSB)
Ax-A0
D7-D0
CE
OE WR (2)
Memory
(LSB)
Ax-A0
D7-D0
CE
OE WR(2)
© 1997 Microchip Technology Inc.
Preliminary
DS30264A-page 41
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