PIC18C601T-E/PT(2001) View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18C601T-E/PT
(Rev.:2001)

High-Performance ROM-less Microcontrollers with External Memory Bus

Microchip Technology 

PIC18C601/801

16.0 ADDRESSABLE UNIVERSAL

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (USART)

The Universal Synchronous Asynchronous Receiver

Transmitter (USART) module is one of the two serial

I/O modules. (USART is also known as a Serial Com-

munications Interface or SCI.) The USART can be con-

figured as a full duplex asynchronous system that can

communicate with peripheral devices, such as CRT ter-

minals and personal computers, or it can be configured

as a half duplex synchronous system that can commu-

nicate with peripheral devices, such as A/D or D/A inte-

grated circuits, serial EEPROMs, etc.

REGISTER 16-1: TXSTA REGISTER

R/W-0

CSRC

bit 7

R/W-0

TX9

R/W-0

TXEN

The USART can be configured in the following modes:

• Asynchronous (full duplex)

• Synchronous - Master (half duplex)

• Synchronous - Slave (half duplex)

The SPEN (RCSTA register) and the TRISC<7> bits

have to be set, and the TRISC<6> bit must be

cleared, in order to configure pins RC6/TX/CK and

RC7/RX/DT as the Universal Synchronous Asynchro-

nous Receiver Transmitter.

Register 16-1 shows the Transmit Status and Control

Register (TXSTA) and Register 16-2 shows the

Receive Status and Control Register (RCSTA).

R/W-0

SYNC

U-0

R/W-0

R-1

R/W-0

—

BRGH TRMT TX9D

bit 0

bit 7

CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care

Synchronous mode:

1 = Master mode (Clock generated internally from BRG)

0 = Slave mode (Clock from external source)

bit 6

TX9: 9-bit Transmit Enable bit

1 = Selects 9-bit transmission

0 = Selects 8-bit transmission

bit 5

TXEN: Transmit Enable bit

1 = Transmit enabled

0 = Transmit disabled

SREN/CREN overrides TXEN in SYNC mode.

bit 4

SYNC: USART Mode Select bit

1 = Synchronous mode

0 = Asynchronous mode

bit 3

Unimplemented: Read as '0'

bit 2

BRGH: High Baud Rate Select bit

Asynchronous mode:

1 = High speed

0 = Low speed

Synchronous mode:

Unused in this mode

bit 1

TRMT: Transmit Shift Register Status bit

1 = TSR empty

0 = TSR full

bit 0

TX9D: 9th bit of Transmit Data. Can be Address/Data bit or a parity bit.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

 2001 Microchip Technology Inc.

Advance Information

DS39541A-page 177

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