PIC18LC601-IL View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LC601-IL

High-Performance ROM-less Microcontrollers with External Memory Bus

Microchip Technology 

20.0 INSTRUCTION SET SUMMARY

The PIC18C601/801 instruction set adds many

enhancements to the previous PIC® MCU instruction

sets, while maintaining an easy migration path from

them.

With few exceptions, instructions are a single program

memory word (16-bits). Each single word instruction is

divided into an OPCODE, which specifies the instruc-

tion type, and one or more operands which further

specify the operation of the instruction.

The instruction set is highly orthogonal and is grouped

into four basic categories:

• Byte-oriented operations

• Bit-oriented operations

• Literal operations

• Control operations

The PIC18C601/801 instruction set summary in

Table 20-2 lists byte-oriented, bit-oriented, literal

and control operations. Table 20-1 shows the opcode

field descriptions.

Most byte-oriented instructions have three operands:

1. The file register (represented by ’f’)

2. The destination of the result

(represented by ’d’)

3. The accessed memory

(represented by ’a’)

The file register designator ‘f’ specifies which file regis-

ter is to be used by the instruction.

The destination designator ‘d’ specifies where the

result of the operation is to be placed. If 'd' is zero, the

result is placed in the WREG register. If 'd' is one, the

result is placed in the file register specified in the

instruction.

All bit-oriented instructions have three operands:

1. The file register (represented by ’f’)

2. The bit in the file register

(represented by ’b’)

3. The accessed memory

(represented by ’a’)

The bit field designator 'b' selects the number of the bit

affected by the operation, while the file register desig-

nator 'f' represents the number of the file in which the

bit is located.

PIC18C601/801

The literal instructions may use some of the following

operands:

• A literal value to be loaded into a file register

(represented by ’k’)

• The desired FSR register to load the literal value

into (represented by ’f’)

• No operand required

(specified by ’—’)

The control instructions may use some of the following

operands:

• A program memory address (represented by ’n’)

• The mode of the Call or Return instructions

(represented by ’s’)

• The mode of the Table Read and Table Write

instructions (represented by ’m’)

• No operand required

(specified by ’—’)

All instructions are a single word, except for four double

word instructions. These four instructions were made

double word instructions so that all the required infor-

mation is available in these 32 bits. In the second word,

the 4 MSbs are 1’s. If this second word is executed as

an instruction (by itself), it will execute as a NOP.

All single word instructions are executed in a single

instruction cycle, unless a conditional test is true, or the

program counter is changed as a result of the instruc-

tion. In these cases, the execution takes two instruction

cycles, with the additional instruction cycle(s) executed

as a NOP.The double word instructions execute in two

instruction cycles.

One instruction cycle consists of four oscillator periods.

Thus, for an oscillator frequency of 4 MHz, the normal

instruction execution time is 1 s. If a conditional test is

true, or the program counter is changed as a result of

an instruction, the instruction execution time is 2 s.

Two word branch instructions (if true) would take 3 s.

Figure 20-1 shows the general formats that the instruc-

tions can have. All examples use the format ‘nnh’ to

represent a hexadecimal number, where ‘h’ signifies

a hexadecimal digit.

The Instruction Set Summary, shown in Table 20-2,

lists the instructions recognized by the Microchip

assembler (MPASMTM).

Section 20.1 provides a description of each instruction.

 2001-2013 Microchip Technology Inc.

Advance Information

DS39541B-page 215

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