PIC18F8520-IPT301 View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F8520-IPT301

64/80-Pin High-Performance, 256 Kbit to 1 MbitEnhanced Flash Microcontrollers with A/D

Microchip Technology 

PIC18F6520/8520/6620/8620/6720/8720

ister .................................................................... 31

SUBFWB .......................................................................... 294

SUBLW ............................................................................ 295

SUBWF ............................................................................ 295

SUBWFB .......................................................................... 296

SWAPF ............................................................................ 296

T

Table Pointer Operations (table) ........................................ 64

TBLRD ............................................................................. 297

TBLWT ............................................................................. 298

Time-out in Various Situations ........................................... 31

Timer0 .............................................................................. 131

16-bit Mode Timer Reads and Writes ...................... 133

Associated Registers ............................................... 133

Clock Source Edge Select (T0SE Bit) ...................... 133

Clock Source Select (T0CS Bit) ............................... 133

Operation ................................................................. 133

Overflow Interrupt .................................................... 133

Prescaler. See Prescaler, Timer0

Timer0 and Timer1 External Clock Requirements ........... 326

Timer1 .............................................................................. 135

16-bit Read/Write Mode ........................................... 138

Associated Registers ............................................... 139

Operation ................................................................. 136

Oscillator .......................................................... 135, 137

Overflow Interrupt ............................................ 135, 138

Special Event Trigger (CCP) ............................ 138, 152

TMR1H Register ...................................................... 135

TMR1L Register ....................................................... 135

Use as a Real-Time Clock ....................................... 138

Timer2 .............................................................................. 141

Associated Registers ............................................... 142

Operation ................................................................. 141

Postscaler. See Postscaler, Timer2

PR2 Register .................................................... 141, 154

Prescaler. See Prescaler, Timer2

SSP Clock Shift ................................................ 141, 142

TMR2 Register ......................................................... 141

TMR2 to PR2 Match Interrupt .................. 141, 142, 154

Timer3 .............................................................................. 143

Associated Registers ............................................... 145

Operation ................................................................. 144

Oscillator .......................................................... 143, 145

Overflow Interrupt ............................................ 143, 145

Special Event Trigger (CCP) .................................... 145

TMR3H Register ...................................................... 143

TMR3L Register ....................................................... 143

Timer4 .............................................................................. 147

Associated Registers ............................................... 148

Operation ................................................................. 147

Postscaler. See Postscaler, Timer4

PR4 Register ............................................................ 147

Prescaler. See Prescaler, Timer4

SSP Clock Shift ........................................................ 148

TMR4 Register ......................................................... 147

TMR4 to PR4 Match Interrupt .......................... 147, 148

Timing Diagrams

A/D Conversion ........................................................ 338

Acknowledge Sequence .......................................... 190

Baud Rate Generator with Clock Arbitration ............ 184

BRG Reset Due to SDA Arbitration During Start Condi-

tion ................................................................... 193

Brown-out Reset (BOR) ........................................... 325

Bus Collision During a Repeated Start Condition (Case

1) ...................................................................... 194

DS39609C-page 372

Bus Collision During a Repeated Start Condition (Case

2) ..................................................................... 194

Bus Collision During a Stop Condition (Case 1) ...... 195

Bus Collision During a Stop Condition (Case 2) ...... 195

Bus Collision During Start Condition (SCL = 0) ....... 193

Bus Collision During Start Condition (SDA only) ..... 192

Bus Collision for Transmit and Acknowledge .......... 191

Capture/Compare/PWM (All CCP Modules) ............ 326

CLKO and I/O .......................................................... 321

Clock Synchronization ............................................. 177

Clock/Instruction Cycle .............................................. 44

Example SPI Master Mode (CKE = 0) ..................... 328

Example SPI Master Mode (CKE = 1) ..................... 329

Example SPI Slave Mode (CKE = 0) ....................... 330

Example SPI Slave Mode (CKE = 1) ....................... 331

External Clock (All Modes except PLL) ................... 320

External Memory Bus for Sleep (Microprocessor Mode)

77

External Memory Bus for TBLRD (Extended Microcon-

troller Mode) ...................................................... 76

External Memory Bus for TBLRD (Microprocessor Mode)

............................................................................ 76

I2C Bus Data ............................................................ 333

I2C Bus Start/Stop Bits ............................................ 332

I2C Master Mode (7 or 10-bit Transmission) ............ 188

I2C Master Mode (7-bit Reception) .......................... 189

I2C Master Mode First Start Bit Timing .................... 185

I2C Slave Mode (10-bit Reception, SEN = 0) .......... 174

I2C Slave Mode (10-bit Reception, SEN = 1) .......... 179

I2C Slave Mode (10-bit Transmission) ..................... 175

I2C Slave Mode (7-bit Reception, SEN = 0) ............ 172

I2C Slave Mode (7-bit Reception, SEN = 1) ............ 178

I2C Slave Mode (7-bit Transmission) ....................... 173

Low-Voltage Detect ................................................. 236

Master SSP I2C Bus Data ........................................ 335

Master SSP I2C Bus Start/Stop Bits ........................ 335

Parallel Slave Port (PIC18F8X20) ........................... 327

Program Memory Read ........................................... 322

Program Memory Write ............................................ 323

PWM Output ............................................................ 154

Repeat Start Condition ............................................ 186

Reset, Watchdog Timer (WDT), Oscillator Start-up Timer

(OST) and Power-up Timer (PWRT) ............... 324

Slave Mode General Call Address Sequence (7 or 10-bit

Address Mode) ................................................ 180

Slave Synchronization ............................................. 163

Slow Rise Time (MCLR Tied to VDD via 1 kOhm Resistor)

............................................................................ 38

SPI Mode (Master Mode) ......................................... 162

SPI Mode (Slave Mode with CKE = 0) ..................... 164

SPI Mode (Slave Mode with CKE = 1) ..................... 164

Stop Condition Receive or Transmit Mode .............. 190

Synchronous Reception (Master Mode, SREN) ...... 210

Synchronous Transmission ..................................... 209

Synchronous Transmission (Through TXEN) .......... 209

Time-out Sequence on POR w/PLL Enabled (MCLR Tied

to VDD via 1 kOhm Resistor) ............................. 38

Time-out Sequence on Power-up (MCLR Not Tied to

VDD)

Case 1 ............................................................... 37

Case 2 ............................................................... 37

Time-out Sequence on Power-up (MCLR Tied to VDD via

1 kOhm Resistor) ............................................... 37

Timer0 and Timer1 External Clock .......................... 325

Timing for Transition Between Timer1 and OSC1 (HS

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