PIC18LF8520-IPT301 View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LF8520-IPT301

64/80-Pin High-Performance, 256 Kbit to 1 MbitEnhanced Flash Microcontrollers with A/D

Microchip Technology 

PIC18F6520/8520/6620/8620/6720/8720

4.6 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 and Q4). The instruction fetch and execute are

pipelined, such that fetch takes one instruction cycle,

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO),

then two cycles are required to complete the instruction

(Example 4-2).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the “Instruction Register” (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3 and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW

1. MOVLW 55h

2. MOVWF PORTB

TCY0

Fetch 1

TCY1

Execute 1

Fetch 2

3. BRA SUB_1

4. BSF PORTA, BIT3 (Forced NOP)

5. Instruction @ address SUB_1

TCY2

Execute 2

Fetch 3

TCY3

TCY4

TCY5

Execute 3

Fetch 4 Flush (NOP)

Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed”

from the pipeline, while the new instruction is being fetched and then executed.

4.7 Instructions in Program Memory

The program memory is addressed in bytes. Instruc-

tions are stored as two bytes or four bytes in program

memory. The Least Significant Byte of an instruction

word is always stored in a program memory location

with an even address (LSB = 0). Figure 4-5 shows an

example of how instruction words are stored in the pro-

gram memory. To maintain alignment with instruction

boundaries, the PC increments in steps of 2 and the

LSB will always read ‘0’ (see Section 4.4 “PCL,

PCLATH and PCLATU”).

The CALL and GOTO instructions have an absolute

program memory address embedded into the

instruction. Since instructions are always stored on

word boundaries, the data contained in the instruction

is a word address. The word address is written to

PC<20:1>, which accesses the desired byte address in

program memory. Instruction #2 in Figure 4-5 shows

how the instruction “GOTO 000006h” is encoded in the

program memory. Program branch instructions, which

encode a relative address offset, operate in the same

manner. The offset value stored in a branch instruction

represents the number of single-word instructions that

the PC will be offset by. Section 24.0 “Instruction Set

Summary” provides further details of the instruction

set.

FIGURE 4-5:

INSTRUCTIONS IN PROGRAM MEMORY

Program Memory

Byte Locations 

Instruction 1: MOVLW

Instruction 2: GOTO

Instruction 3: MOVFF

055h

000006h

123h, 456h

LSB = 1

0Fh

EFh

F0h

C1h

F4h

LSB = 0

55h

03h

00h

23h

56h

Word Address



000000h

000002h

000004h

000006h

000008h

00000Ah

00000Ch

00000Eh

000010h

000012h

000014h

 2003-2013 Microchip Technology Inc.

DS39609C-page 45

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