PIC18LF8520-IPT301 View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LF8520-IPT301

64/80-Pin High-Performance, 256 Kbit to 1 MbitEnhanced Flash Microcontrollers with A/D

Microchip Technology 

PIC18F6520/8520/6620/8620/6720/8720

EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

PROGRAM_MEMORY

BSF

BCF

BSF

BCF

MOVLW

MOVWF

Required MOVLW

Sequence MOVWF

BSF

NOP

BSF

DECFSZ

BRA

BCF

EECON1, EEPGD

EECON1, CFGS

EECON1, WREN

INTCON, GIE

55h

EECON2

AAh

EECON2

EECON1, WR

INTCON, GIE

COUNTER_HI

PROGRAM_LOOP

EECON1, WREN

; point to Flash program memory

; access Flash program memory

; enable write to memory

; disable interrupts

; write 55H

; write AAH

; start program (CPU stall)

; re-enable interrupts

; loop until done

; disable write to memory

5.5.2 WRITE VERIFY

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in applications where excessive writes

can stress bits near the specification limit.

5.5.3

UNEXPECTED TERMINATION OF

WRITE OPERATION

If a write is terminated by an unplanned event, such as

loss of power or an unexpected Reset, the memory

location just programmed should be verified and repro-

grammed if needed. The WRERR bit is set when a

write operation is interrupted by a MCLR Reset, or a

WDT Time-out Reset during normal operation. In these

situations, users can check the WRERR bit and rewrite

the location.

5.5.4

PROTECTION AGAINST

SPURIOUS WRITES

To protect against spurious writes to Flash program

memory, the write initiate sequence must also be

followed. See Section 23.0 “Special Features of the

CPU” for more detail.

5.6 Flash Program Operation During

Code Protection

See Section 23.0 “Special Features of the CPU” for

details on code protection of Flash program memory.

TABLE 5-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Name

Bit 7

Bit 6

Bit 5 Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

TBLPTRU

—

—

bit 21 Program Memory Table Pointer Upper Byte

(TBLPTR<20:16>)

TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)

TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)

TABLAT Program Memory Table Latch

INTCON GIE/GIEH PEIE/GIEL TMR0IE INTE RBIE TMR0IF INTF

EECON2 EEPROM Control Register 2 (not a physical register)

EECON1 EEPGD CFGS

—

FREE WRERR WREN

WR

IPR2

—

CMIP

—

EEIP BCLIP LVDIP TMR3IP

PIR2

—

CMIF

—

EEIF BCLIF LVDIF TMR3IF

PIE2

—

CMIE

—

EEIE BCLIE LVDIE TMR3IE

Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ‘0’.

Shaded cells are not used during Flash/EEPROM access.

RBIF

RD

CCP2IP

CCP2IF

CCP2IE

--00 0000 --00 0000

0000 0000

0000 0000

0000 0000

0000 0000

—

xx-0 x000

---1 1111

---0 0000

---0 0000

0000 0000

0000 0000

0000 0000

0000 0000

—

uu-0 u000

---1 1111

---0 0000

---0 0000

 2003-2013 Microchip Technology Inc.

DS39609C-page 69

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