PSD913G3V-C-90JI View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

PSD913G3V-C-90JI

Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs

STMicroelectronics 

Preliminary Information

PSD9XX Family

The

PSD9XX

Functional

Blocks

(cont.)

9.2.1 Decode PLD (DPLD)

The DPLD, shown in Figure 10, is used for decoding the address for internal PSD

components. The DPLD can generate the following chip selects:

• 8 sector selects for the main Flash memory (three product terms each)

• 4 sector selects for the Secondary Flash memory (three product terms each)

• 1 internal SRAM select (two product terms)

• 1 internal CSIOP select (select PSD registers, one product term)

Inputs to the DPLD chip selects may include address inputs, Page Register inputs and

other user defined external inputs from Ports A, B, C or D.

9.2.2 General Purpose PLD (GPLD)

The General Purpose PLD implements user defined system combinatorial logic function

or chip selects for external devices. Figure 11 shows how the GPLD is connected to the

I/O Ports. The GPLD has 19 outputs and each are routed to a port pin. The port pin can

also be configured as input tot eh GPLD. When it is not used as GPLD output or input, the

pin can be configured to perform other I/O functions.

The GPLD outputs are identical except in the number of available product terms for logic

implementation. Select the pin that can best meet the product term requirement of your

logic function or chip selects. The outputs can be configured as active high or low outputs.

Table 16 shows the number of product terms that are assigned to the PLD outputs on the

I/O Ports. When PSD9XX is connected to a MCU with non-multiplexed bus, Port A will be

configured as the Data Port and the GPLD outputs will not be available.

Table 16. GPLD Output Product Term

GPLD Output on Port Pin Number of Product Terms

Port A, pins PA0-3

3

Port A, pins PA4-7

9

Port B, pins PB0-3

4

Port B, pins PB4-7

7

Port D, pins PD0-2

1

33

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