ST10F269Z2QX View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST10F269Z2QX Datasheet PDF : 161 Pages
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Figure 59 : Minimum External Reset Circuitry
VDD
R0
+
C0
ST10F269
RPD
RSTOUT
RSTIN
+ b)
C1
ST10F269Z2Qx
External
Hardware
a) a) Manual hardware reset1
b) For automatic power-up and
interruptible power-down mode
Figure 60 : External Reset Hardware Circuitry
VDD
R0
+
C0
RSTOUT
ST10F269
RPD
VDD
RSTIN
R2
External
Hardware D1
D2
Open - drain
Inverter
External
Reset Source
VDD
R1
+
C1
Table 29 : PORT0 Latched Configuration for the Different Resets
PORT0
X: Pin is sampled
-: Pin is not sampled
Sample event
Software Reset
- - - XXXXXXX - - - - - -
Watchdog Reset
- - - XXXXXXX - - - - - -
Short Hardware Reset
- - - XXXXXXXXXXXXX
Long Hardware Reset
XXXXXXXXXXXXXXXX
Power-On Reset
XXXXXXXXXXXXXXXX
Table 30 : PORT0 Bits Latched into the Different Registers After Reset
PORT0 bit
Nebr.
h7
h6
h5
h4
h3
h2
h1
h0
I7
I6
I5
I4
I3
I2
I1
I0
PORT0 bit CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL CSSEL WRC BUSTYP BUSTYP R
BSL
R
Name
R ADP EMU
RP0H 2
X1
X1
X1
X1
X1
X1
X1
X 1 CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL CSSEL WRC
SYSCON
X1
X1
X1
X1
X1
X 1 BYTDIS 3 X 1 WRCFG 3 X 1
X1
X1
X1
X1
X1
X1
BUSCON0 X 1
X1
X1
X1
-
BUS ALE
-
BTYP BTYP
X1
X1
X1
X1
X1
X1
ACT0 4 CTL0 4
Internal
Logic
To Clock Generator
To Port 4 Logic To Port 6 Logic X 1
X1
X1
X 1 Internal X 1
X 1 Internal Internal
Notes: 1. Not latched from PORT0.
2. Only RP0H low byte is used and the bit-fields are latched from PORT0 high byte to RP0H low byte.
3. Indirectly depend on PORT0.
4. Bits set if EA pin is 1.
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