ST10F269Z2QX View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST10F269Z2QX

16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM

STMicroelectronics 

ST10F269Z2Qx

Figure 23 : PORT1 I/O and Alternate Functions

Alternate Function

P1H

PORT1

P1L

P1H.7

P1H.6

P1H.5

P1H.4

P1H.3

P1H.2

P1H.1

P1H.0

P1L.7

P1L.6

P1L.5

P1L.4

P1L.3

P1L.2

P1L.1

P1L.0

General Purpose Input/Output

a)

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

8/16-bit Demultiplexed Bus

b)

CC27IO

CC26IO

CC25IO

CC24IO

CAPCOM2 Capture Inputs only

When an external bus mode is enabled, the

direction of the port pin and the loading of data

into the port output latch are controlled by the bus

controller hardware.

The input of the port Buffer latch is disconnected

from the internal bus and is switched to the line

labeled “Alternate Data Output” via a multiplexer.

The alternate data is the 16-bit intra-segment

address. While an external bus mode is enabled,

the user software should not write to the port

output latch, otherwise unpredictable results may

occur. When the external bus modes are disabled,

the contents of the direction register last written by

the user becomes active.

The Figure 24 shows the structure of a PORT1

pin.

Figure 24 : Block Diagram of a PORT1 Pin

Write DP1H.y / DP1L.y

Direction

Latch

“1”

1

MUX

0

Read DP1H.y / DP1L.y

Alternate

Function

Enable

Alternate

Data

Output

Write P1H.y / P1L.y

Port Output

Latch

Port Data

Output

1

MUX

0

Output

Buffer

P1H.y

P1L.y

Read P1H.y / P1L.y

1

MUX

0

Clock

Input

Latch

y = 7...0

65/161

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