ST20-GP1 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST20-GP1

GPS PROCESSOR

STMicroelectronics 

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 ST20-GP1 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Digital signal processing module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1 DSP module registers .......................................................................................................................... 13

4 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1 Registers .............................................................................................................................................. 18

4.2 Processes and concurrency ................................................................................................................ 19

4.3 Priority .................................................................................................................................................. 21

4.4 Process communications ..................................................................................................................... 21

4.5 Timers .................................................................................................................................................. 22

4.6 Traps and exceptions .......................................................................................................................... 23

5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.1 Interrupt vector table ............................................................................................................................ 29

5.2 Interrupt handlers ................................................................................................................................. 29

5.3 Interrupt latency ................................................................................................................................... 30

5.4 Pre-emption and interrupt priority ........................................................................................................ 30

5.5 Restrictions on interrupt handlers ........................................................................................................ 30

5.6 Interrupt configuration registers ........................................................................................................... 31

6 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.1 Instruction cycles ................................................................................................................................. 34

6.2 Instruction characteristics .................................................................................................................... 35

6.3 Instruction set tables ............................................................................................................................ 36

7 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.1 System memory use ............................................................................................................................ 45

7.2 Boot ROM ............................................................................................................................................ 46

7.3 Internal peripheral space ..................................................................................................................... 46

8 Memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.1 SRAM .................................................................................................................................................. 49

9 Programmable memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9.1 EMI signal descriptions ........................................................................................................................ 51

9.2 Strobe allocation .................................................................................................................................. 52

9.3 External accesses ................................................................................................................................ 52

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