ST20-GP1 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST20-GP1

GPS PROCESSOR

STMicroelectronics 

ST20-GP1

6.2 Instruction characteristics

The Primary Instructions Table 6.3 gives the basic function code. Where the operand is less than

16, a single byte encodes the complete instruction. If the operand is greater than 15, one prefix

instruction (pfix) is required for each additional four bits of the operand. If the operand is negative

the first prefix instruction will be nfix. Examples of pfix and nfix coding are given in Table 6.1.

Mnemonic

Function code

ldc

#3

#4

ldc

#35

is coded as

pfix #3

#2

ldc

#5

#4

ldc

#987

is coded as

pfix #9

#2

pfix #8

#2

ldc

#7

#4

ldc

-31 ( ldc #FFFFFFE1)

is coded as

nfix #1

#6

ldc

#1

#4

Memory code

#43

#23

#45

#29

#28

#47

#61

#41

Table 6.1 Prefix coding

Any instruction which is not in the instruction set tables is an invalid instruction and is flagged

illegal, returning an error code to the trap handler, if loaded and enabled.

The Notes column of the tables indicates the descheduling and error features of an instruction as

described in Table 6.2.

Ident

E

L

S

O

I

A

D

T

Feature

Instruction can set an IntegerError trap

Instruction can cause a LoadTrap trap

Instruction can cause a StoreTrap trap

Instruction can cause an Overflow trap

Interruptible instruction

Instruction can be aborted and later restarted.

Instruction can deschedule

Instruction can timeslice

Table 6.2 Instruction features

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