ST72E311 ST72T311
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 36. SCI Baud Rate and Extended Prescaler Block Diagram
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
ETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
ERPR
EXTENDED RECEIVER PRESCALER REGISTER
fCPU
/16
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
/2
/PR
TRANSMITTER RATE
CONTROL
BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
TRANSMITTER
CLOCK
RECEIVER
CLOCK
58/101
58