Block description
6
Block description
STULPI01A - STULPI01B
The STULPI01 integrates a comparator for the VBUS, ID line detector, differential HS data
driver, differential and single-ended receivers, low dropout voltage regulators, and control
logic.
The STULPI01 provides a complete solution for connection of a digital USB
host/device/OTG controller to a USB bus.
6.1
Oscillator and PLL
An external clock (digital square wave 1V8VIO referred) driven into XI must be used (version
STULPI01A or STULPI01B).
The PLL internally produces all frequencies needed for operation:
● 60 MHz clock for the UTMI core and ULPI interface controller
● 1.5 MHz for low speed USB data
● 12 MHz for full speed USB data
● 480 MHz for high speed USB data
● Other internal frequencies for data conversion and data recovery
6.2
Voltage reference
This block provides the precise reference voltage needed by internal circuit.
It requires a 12 kΩ +/- 1% resistor connected to the RREF pin.
6.3
Power-on-reset (POR)
The power-on-reset circuit generates a reset pulse upon power-up which is used to initialize
the entire digital logic. Power-on-reset senses the V3V3V and V1V2V voltage.
During power-on-reset pulse, the ULPI pins are in a high impedance state with pull-
down/pull-up resistors disabled.
6.4
UTMI + CORE
This is the digital heart of the chip and performs the bit-stuffing, NRZI decoding and serial-
to-parallel conversion during receive and the reverse operation during transmit for HS and
FS/LS.
6.5
ULPI wrapper
This implements the ULPI related protocol and conversion from UTMI+ to ULPI interface.
This block also implements the interrupt logic and complete ULPI register set.
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