PF28F1604CB110 View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

PF28F1604CB110

Intel® Advanced+ Boot Block Flash Memory (C3)

Intel 

C3 SCSP Flash Memory

Figure 12. Example Power Supply Configurations

System Supply

12 V Supply

VCC

VPP

10 ≤ KΩ

12 V Fast Programming

Absolute Write Protection With V PP ≤ VPPLK

System Supply

(Note 1)

VCC

VPP

12 V Supply

Low Voltage and 12 V Fast Programming

System Supply

VCC

Prot#

VPP

(Logic Signal)

Low-Voltage Programming

Absolute Write Protection via Logic Signal

System Supply

VCC

VPP

Low-Voltage Programming

Note: 1. A resistor can be used if the F-VCC supply can sink adequate current based on resistor value.

7.3

Noise Reduction

SCSP memory’s power switching characteristics require careful device decoupling. System

designers should consider three supply current issues for both the flash and SRAM:

• Standby current levels (ICCS)

• Read current levels (ICCR)

• Transient peaks produced by falling and rising edges of F-CE#, S-CS1#, and S-CS2.

Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-

line control and proper decoupling capacitor selection will suppress these transient voltage peaks.

Each device should have a capacitors between individual power (F-VCC, F-VCCQ, F-VPP,

S-VCC) and ground (GND) signals. High-frequency, inherently low-inductance capacitors should

be placed as close as possible to the package leads.

Noise issues within a system can cause devices to operate erratically if it is not adequately filtered.

In order to avoid any noise interaction issues within a system, it is recommended that the design

contain the appropriate number of decoupling capacitors in the system. Noise issues can also be

reduced if leads to the device are kept very short, in order to reduce inductance.

Decoupling capacitors between VCC and VSS reduce voltage spikes by supplying the extra current

needed during switching. Placing these capacitors as close to the device as possible reduces line

inductance. The capacitors should be low inductance capacitors; surface mount capacitors typically

exhibit lower inductance.

It is highly recommended that systems use a 0.1 µf capacitor for each of the D9, D10, A10 and E4

grid ballout locations (see Figure 1 “66-Ball SCSP Package Ballout” on page 8 for ballout). These

capacitors are necessary to avoid undesired conditions created by excess noise. Smaller capacitors

can be used to decouple higher frequencies.

Datasheet

Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family

Order Number: 252636, Revision: 004

26 Aug 2005

43

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