Z86M1720ASC View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z86M1720ASC

PCMCIA Interface Solution

Zilog 

Z86017/Z16017 PCMCIA Interface Solution

Product Specification

25

Peripheral Control Signals

• POR (Input, Schmitt-Triggered, 100K Pull-Up)

Local Power-On Reset signal. A 0.1mF capacitor is recommended on

this pin to GND to generate a POR.

• M_PINT (Output, Tri-State, 8 mA)

Interrupt to local microprocessor

• PC_MCLK_IN (Input, Schmitt-Triggered)

Master Clock In. This is an input signal. This clock signal is used to

generate all internal timing. All local bus signals are asynchronous to

this clock.

• EXTP_STSCHG/RES2 (Input, 100K Pull-Up)

Status Change Input. This signal outputs the value of the status

changed line on the PCMCIA bus if enabled in the CCR register, or it

is an input for bit 7 (RSVDEVT3) in CCR4.

• EXTP_AUDIO (Input 100K Pull-Up)

Audio Input. This input signal reflects the audio output. This signal is

active High, and the Speaker output on the PCMCIA bus is active

Low.

• EXTP_PWDN (Output, 8 mA)

Power Down Output. This signal reflects the state of the Power Down

bit in the CCR.

• VSS (Input)

Ground.

• VDD (Input)

Supply Voltage.

PCMCIA Interface Overview

PS012002-1201

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