Z80230 View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z80230

Zilog SCC Serial Communication Controller

Zilog 

Application Note

Interfacing Z80® CPUs to the Z8500 Peripheral Family

EXTERNAL INTERFACE LOGIC (Continued)

Figure 11. Z80H to Z8500/Z8500A Peripheral Interrupt Acknowledge Interface Logic

During RETI cycles, the IEO line from the Z8500 peripherals

does not change state as in the Z80 peripherals. As long as

the peripherals are at the top of the daisy chain, propagation

delays are minimized.

The logic necessary to create the control signals for both

Z80 and Z8500 peripherals is shown in Figure 9. This logic

delays the generation of /IORQ to the Z80 peripherals by

the same amount of time necessary to generate /READ for

the Z8500 peripherals. Timing for this logic during an

Interrupt Acknowledge cycle is depicted in Figure 10.

6-18

UM010901-0601

Share Link: