AD9859(RevB) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9859 Datasheet PDF : 24 Pages
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AD9859
There are two phases to a communication cycle with the
AD9859. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9859, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9859 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication cycle.
The Phase 1 instruction byte defines whether the upcoming data
transfer is read or write and the serial address of the register
being accessed.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9859. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9859
and the system controller. The number of bytes transferred
Data Sheet
during Phase 2 of the communication cycle is a function of the
register being accessed. For example, when accessing the Control
Function Register 2, which is three bytes wide, Phase 2 requires that
three bytes be transferred. If accessing the frequency tuning word,
which is four bytes wide, Phase 2 requires that four bytes be
transferred. After transferring all data bytes per the instruction,
the communication cycle is completed.
At the completion of any communication cycle, the AD9859
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle. All
data input to the AD9859 is registered on the rising edge of
SCLK. All data is driven out of the AD9859 on the falling edge
of SCLK. Figure 21 through Figure 24 are useful in understand-
ing the general operation of the AD9859 serial port.
CS
SCLK
SDIO
I7
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
I6 I5 I4 I3 I2 I1 I0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 21. Serial Port Write Timing—Clock Stall Low
CS
SCLK
SDIO
I7
SDO
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
I6 I5 I4 I3 I2 I1 I0
DON'T CARE
DO 7 DO 6 DO 5 DO 4 DO 3 DO 2 DO 1 DO 0
Figure 22. 3-Wire Serial Port Read Timing—Clock Stall Low
CS
SCLK
SDIO
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
I7 I6 I5 I4 I3 I2 I1 I0
D7
D6 D5 D4 D3 D2 D1
D0
Figure 23. Serial Port Write Timing—Clock Stall High
CS
SCLK
SDIO
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
I7 I6 I5 I4 I3 I2 I1 I0
DO 7 DO 6 DO 5 DO 4 DO 3 DO 2 DO 1 DO 0
Figure 24. 2-Wire Serial Port Read Timing—Clock Stall High
Rev. B | Page 20 of 24
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