Lattice Semiconductor
Pinout Information
MachXO Family Data Sheet
Pin Information Summary
LCMXO256C/E
Pin Type
100 TQFP
100 csBGA
100 TQFP
Single Ended User I/O
78
78
74
Differential Pair User I/O1
38
38
17
Muxed
6
6
6
TAP
4
4
4
Dedicated (Total Without Supplies)
5
5
5
VCC
2
2
2
VCCAUX
1
1
1
Bank0
3
3
2
VCCIO
Bank1
3
3
2
Bank2
—
—
2
Bank3
—
—
2
GND
8
8
10
NC
0
0
0
Bank0
41/20
41/20
18/5
Single Ended/Differential I/O Bank1
37/18
37/18
21/4
per Bank
Bank2
—
—
14/2
Bank3
—
—
21/6
1. These devices support emulated LVDS outputs. LVDS inputs are not supported.
144 TQFP
113
43
6
4
5
4
2
2
2
2
2
12
0
29/10
30/11
24/9
30/13
LCMXO640C/E
100 csBGA
74
17
6
4
5
2
1
2
2
2
2
10
0
18/5
21/4
14/2
21/6
132 csBGA
101
42
6
4
5
4
2
2
2
2
2
12
0
26/11
27/12
21/9
27/10
256 ftBGA
159
79
6
4
5
4
2
4
4
4
4
18
52
42/21
40/20
36/18
40/20
LCMXO1200C/E
Pin Type
100 TQFP 144 TQFP 132 csBGA
Single Ended User I/O
73
113
101
Differential Pair User I/O1
27
48
42
Muxed
6
6
6
TAP
4
4
4
Dedicated (Total Without Supplies)
5
5
5
VCC
4
4
4
VCCAUX
2
2
2
Bank0
1
1
1
Bank1
1
1
1
Bank2
1
1
1
VCCIO
Bank3
1
1
1
Bank4
1
1
1
Bank5
1
1
1
Bank6
1
1
1
Bank7
1
1
1
GND
8
12
12
NC
0
0
0
Bank0
10/3
14/6
13/5
Bank1
8/2
15/7
13/5
Bank2
10/4
15/7
13/6
Single Ended/Differential I/O Bank3
11/5
15/7
14/7
per Bank
Bank4
8/3
14/5
13/5
Bank5
5/2
10/4
8/2
Bank6
10/3
15/6
13/6
Bank7
11/5
15/6
14/6
1. These devices support on-chip LVDS buffers for left and right I/O Banks.
256 ftBGA
211
105
6
4
5
4
2
2
2
2
2
2
2
2
2
18
0
26/13
28/14
26/13
28/14
27/13
22/11
28/14
26/13
100 TQFP
73
30
6
4
5
2
2
1
1
1
1
1
1
1
1
8
0
9/3
9/3
10/4
11/5
8/3
5/2
10/4
11/5
LCMXO2280C/E
144 TQFP 132 csBGA 256 ftBGA
113
101
211
47
41
105
6
6
6
4
4
4
5
5
5
4
4
4
2
2
2
1
1
2
1
1
2
1
1
2
1
1
2
1
1
2
1
1
2
1
1
2
1
1
2
12
12
18
0
0
0
13/6
12/5
24/12
16/7
14/5
30/15
15/7
13/6
26/13
15/7
14/7
28/14
14/4
13/4
29/14
10/4
8/2
20/10
15/6
13/6
28/14
15/6
14/6
26/13
324 ftBGA
271
134
6
4
5
6
2
2
2
2
2
2
2
2
2
24
0
34/17
36/18
34/17
34/17
35/17
30/15
34/17
34/17
4-2