M38510M2-XXXSP View Datasheet(PDF) - Renesas Electronics

Part Name

Description

Manufacturer

M38510M2-XXXSP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Renesas Electronics 

3851 Group (Built-in 24 KB or more ROM)

INTERRUPTS

Interrupts occur by 17 : seven external, nine internal, and one soft-

ware.

Interrupt Control

Each interrupt is controlled by an interrupt request bit, an interrupt

enable bit, and the interrupt disable flag except for the software in-

terrupt set by the BRK instruction. An interrupt occurs if the

corresponding interrupt request and enable bits are “1” and the in-

terrupt disable flag is “0”.

Interrupt enable bits can be set or cleared by software.

Interrupt request bits can be cleared by software, but cannot be

set by software.

The BRK instruction cannot be disabled with any flag or bit. The I

(interrupt disable) flag disables all interrupts except the BRK in-

struction interrupt.

When several interrupts occur at the same time, the interrupts are

received according to priority.

Interrupt Operation

By acceptance of an interrupt, the following operations are auto-

matically performed:

1. The contents of the program counter and the processor status

register are automatically pushed onto the stack.

2. The interrupt disable flag is set and the corresponding interrupt

request bit is cleared.

3. The interrupt jump destination address is read from the vector

table into the program counter.

Notes

When setting the followings, the interrupt request bit may be set to

“1”.

•When setting external interrupt active edge

Related register: Interrupt edge selection register (address 003A16)

Timer XY mode register (address 002316)

•When switching interrupt sources of an interrupt vector address

where two or more interrupt sources are allocated

Related register: Interrupt edge selection register (address 003A16)

When not requiring for the interrupt occurrence synchronized with

these setting, take the following sequence.

(1) Set the corresponding interrupt enable bit to “0” (disabled).

(2) Set the interrupt edge select bit or the interrupt source select

bit.

(3) Set the corresponding interrupt request bit to “0” after 1 or

more instructions have been executed.

(4) Set the corresponding interrupt enable bit to “1” (enabled).

Rev.1.01 Oct 15, 2003 page 17 of 89

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