M38515F9-SP View Datasheet(PDF) - Renesas Electronics

Part Name

Description

Manufacturer

M38515F9-SP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Renesas Electronics 

3851 Group (Built-in 24 KB or more ROM)

Example of Master Transmission

An example of master transmission in the standard clock mode, at

the SCL frequency of 100 kHz and in the ACK return mode is

shown below.

(1) Set a slave address in the high-order 7 bits of the I2C ad-

dress register (address 002C16) and “0” into the RWB bit.

(2) Set the ACK return mode and SCL = 100 kHz by setting

“8516” in the I2C clock control register (address 002F16).

(3) Set “0016” in the I2C status register (address 002D16) so that

transmission/reception mode can become initializing condi-

tion.

(4) Set a communication enable status by setting “0816” in the

I2C control register (address 002E16).

(5) Confirm the bus free condition by the BB flag of the I2C status

register (address 002D16).

(6) Set the address data of the destination of transmission in the

high-order 7 bits of the I2C data shift register (address

002B16) and set “0” in the least significant bit.

(7) Set “F016” in the I2C status register (address 002D16) to gen-

erate a START condition. At this time, an SCL for 1 byte and

an ACK clock automatically occur.

(8) Set transmit data in the I2C data shift register (address

002B16). At this time, an SCL and an ACK clock automatically

occur.

(9) When transmitting control data of more than 1 byte, repeat

step (8).

(10) Set “D016” in the I2C status register (address 002D16) to gen-

erate a STOP condition if ACK is not returned from slave

reception side or transmission ends.

Example of Slave Reception

An example of slave reception in the high-speed clock mode, at

the SCL frequency of 400 kHz, in the ACK non-return mode and

using the addressing format is shown below.

(1) Set a slave address in the high-order 7 bits of the I2C ad-

dress register (address 002C16) and “0” in the RWB bit.

(2) Set the no ACK clock mode and SCL = 400 kHz by setting

“2516” in the I2C clock control register (address 002F16).

(3) Set “0016” in the I2C status register (address 002D16) so that

transmission/reception mode can become initializing condi-

tion.

(4) Set a communication enable status by setting “0816” in the

I2C control register (address 002E16).

(5) When a START condition is received, an address comparison

is performed.

(6) • When all transmitted addresses are “0” (general call):

AD0 of the I2C status register (address 002D16) is set to “1”

and an interrupt request signal occurs.

• When the transmitted addresses agree with the address set

in (1):

ASS of the I2C status register (address 002D16) is set to “1”

and an interrupt request signal occurs.

• In the cases other than the above AD0 and AAS of the I2C

status register (address 002D16) are set to “0” and no inter-

rupt request signal occurs.

(7) Set dummy data in the I2C data shift register (address

002B16).

(8) When receiving control data of more than 1 byte, repeat step

(7).

(9) When a STOP condition is detected, the communication

ends.

Rev.1.01 Oct 15, 2003 page 38 of 89

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