M95512-DRMB3/AB View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M95512-DRMB3/AB

512 Kbit serial SPI bus EEPROM with high-speed clock

STMicroelectronics 

M95512-W, M95512-R

Instructions

6.9

Read Lock Status (available only in M95512-DR devices)

The Read Lock Status instruction (see Table 4) allows to check if the Identification Page is

locked (or not) in read-only mode. The Read Lock Status sequence is defined with the Chip

Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted

in on Serial Data input (D). Address bit A10 must be 1, all other address bits are Don't Care.

The Lock bit is the LSB (least significant bit) of the byte read on Serial Data output (Q). It is

at ‘1’ when the lock is active and at ‘0’ when the lock is not active. If Chip Select (S)

continues to be driven low, the same data byte is shifted out. The read cycle is terminated by

driving Chip Select (S) high.

The instruction sequence is shown in Figure 17.

Figure 17. Read Lock Status sequence

3

                      

#

)NSTRUCTION

BITADDRESS

$

  



-3"

(IGHIMPEDANCE

1

$ATA/UT

$ATA/UT

 

-3"

!I

6.10

Lock ID (available only in M95512-DR devices)

The Lock ID instruction permanently locks the Identification Page in read-only mode. Before

this instruction can be accepted, a Write Enable (WREN) instruction must have been

executed. The Lock ID instruction is issued by driving Chip Select (S) low, sending the

instruction code, the address and a data byte on Serial Data input (D), and driving Chip

Select (S) high. In the address sent, A10 must be equal to 1, all other address bits are Don't

Care. The data byte sent must be equal to the binary value xxxx xx1x, where x = Don't Care.

Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in

the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,

the Lock ID instruction is not executed.

Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed write

cycle whose duration is tW (specified in Table 17 and Table 18). The instruction sequence is

shown in Figure 18.

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