RC48F2P0ZBQ0 View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

RC48F2P0ZBQ0

Intel StrataFlash® Embedded Memory (P30)

Intel 

1-Gbit P30 Family

Figure 21.

CLK [C]

Address [A]

ADV# [V]

Synchronous Burst-Mode Four-Word Read Timing

y

R302

R301 R306

R2

R101

A

R105

R106

R102

R303

CE# [E]

OE# [G]

WAIT [T]

R3

R15

R307

R8

R9

R17

Data [D/Q]

R4

R7

R304

R304

R305

Q0

Q1

R10

Q2

Q3

Note: WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during

initial latency and deasserted during valid data (RCR[10] = 0, Wait asserted low).

7.4

AC Write Specifications

Table 18.

AC Write Specifications (Sheet 1 of 2)

Num Symbol

W1

W2

W3

W4

W5

W6

W7

W8

W9

W10

W11

W12

W13

tPHWL

tELWL

tWLWH

tDVWH

tAVWH

tWHEH

tWHDX

tWHAX

tWHWL

tVPWH

tQVVL

tQVBL

tBHWH

Parameter

RST# high recovery to WE# low

CE# setup to WE# low

WE# write pulse width low

Data setup to WE# high

Address setup to WE# high

CE# hold from WE# high

Data hold from WE# high

Address hold from WE# high

WE# pulse width high

VPP setup to WE# high

VPP hold from Status read

WP# hold from Status read

WP# setup to WE# high

Min

Max Units Notes

150

-

ns

1,2,3

0

-

ns

1,2,3

50

-

ns

1,2,4

50

-

ns

50

-

ns

0

-

ns

1,2

0

-

ns

0

-

ns

20

-

ns

1,2,5

200

-

ns

1,2,3,7

0

-

ns

0

-

ns

1,2,3,7

200

-

ns

Datasheet

Intel StrataFlash® Embedded Memory (P30)

Order Number: 306666, Revision: 001

April 2005

41

Share Link: