PIC16LF1827T-E/SS View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LF1827T-E/SS

18/20/28-Pin Flash Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC16F/LF1826/27

9.1.1 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a

SLEEP instruction

- SLEEP instruction will execute as a NOP.

- WDT and WDT prescaler will not be cleared

- TO bit of the STATUS register will not be set

- PD bit of the STATUS register will not be

cleared.

• If the interrupt occurs during or after the execu-

tion of a SLEEP instruction

- SLEEP instruction will be completely exe-

cuted

- Device will immediately wake-up from Sleep

- WDT and WDT prescaler will be cleared

- TO bit of the STATUS register will be set

- PD bit of the STATUS register will be cleared.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes. To

determine whether a SLEEP instruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

FIGURE 9-1:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

OSC1(1)

CLKOUT(2)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

TOST(3)

Interrupt flag

GIE bit

(INTCON reg.)

Instruction Flow

PC

PC

Instruction

Fetched

Inst(PC) = Sleep

Instruction

Executed

Inst(PC - 1)

Processor in

Sleep

PC + 1

Inst(PC + 1)

Sleep

PC + 2

Interrupt Latency(4)

PC + 2

Inst(PC + 2)

Inst(PC + 1)

PC + 2

Dummy Cycle

0004h

Inst(0004h)

Dummy Cycle

0005h

Inst(0005h)

Inst(0004h)

Note 1:

2:

3:

4:

XT, HS or LP Oscillator mode assumed.

CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference.

TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes.

GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register on

Page

INTCON

GIE

PEIE

TMR0IE

INTE

IOCIE TMR0IF

INTF

IOCIF

91

IOCBF

IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0

134

IOCBN

IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0

134

IOCBP

IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0

134

PIE1

TMR1GIE ADIE

RCIE

TXIE

SSP1IE CCP1IE TMR2IE TMR1IE

92

PIE2

OSFIE

C2IE

C1IE

EEIE

BCL1IE

—

—

CCP2IE(1)

93

PIE4(1)

—

—

—

—

—

—

BCL2IE SSP2IE

95

PIR1

TMR1GIF ADIF

RCIF

TXIF

SSP1IF CCP1IF TMR2IF TMR1IF

96

PIR2

OSFIF

C2IF

C1IF

EEIF

BCL1IF

—

—

CCP2IF(1)

97

PIR4(1)

—

—

—

—

—

—

BCL2IF SSP2IF

99

STATUS

—

—

—

TO

PD

Z

DC

C

23

WDTCON

—

—

WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN

105

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-down mode.

Note 1: PIC16F/LF1827 only.

DS41391C-page 102

Preliminary

 2010 Microchip Technology Inc.

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