PIC16F1826-E/SO View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16F1826-E/SO Datasheet PDF : 406 Pages
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PIC16F/LF1826/27
After the “BSF EECON1,WR” instruction, the processor
requires two cycles to set up the write operation. The
user must place two NOP instructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms, only during the cycle in which the write
takes place (i.e., the last word of the block write). This
is not Sleep mode as the clocks and peripherals will
continue to run. The processor does not stall when
LWLO = 1, loading the write latches. After the write
cycle, the processor will resume operation with the third
instruction after the EECON1 write instruction.
FIGURE 11-2:
BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES
75
07
0
EEDATH
EEDATA
6
8
First word of block
to be written
Last word of block
to be written
14
14
14
14
EEADRL<4:0> = 00000 EEADRL<4:0> = 00001
EEADRL<4:0> = 00010
EEADRL<4:0> = 11111
Buffer Register
Buffer Register
Buffer Register
Buffer Register
Program Memory
2010 Microchip Technology Inc.
Preliminary
DS41391C-page 113
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