PIC16F1826-E/SO View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16F1826-E/SO Datasheet PDF : 406 Pages
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PIC16F/LF1826/27
TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 0
000h(2) INDF0
001h(2) INDF1
002h(2)
003h(2)
004h(2)
005h(2)
006h(2)
007h(2)
008h(2)
009h(2)
00Ah(2)
00Bh(2)
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
—
—
—
TO
PD
Z
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR4
BSR3
BSR2
Working Register
—
Write Buffer for the upper 7 bits of the Program Counter
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
DC
BSR1
INTF
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
C
BSR0
IOCIF
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
00Ch PORTA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0 xxxx xxxx xxxx xxxx
00Dh PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0 xxxx xxxx xxxx xxxx
00Eh
—
Unimplemented
—
—
00Fh
—
Unimplemented
—
—
010h
—
Unimplemented
—
—
011h
012h
013h
014h
PIR1
PIR2
PIR3(1)
PIR4(1)
TMR1GIF
OSFIF
—
—
ADIF
C2IF
—
—
RCIF
C1IF
CCP4IF
—
TXIF
EEIF
CCP3IF
—
SSP1IF
BCL1IF
TMR6IF
—
CCP1IF
—
—
—
TMR2IF
—
TMR4IF
BCL2IF
TMR1IF 0000 0000 0000 0000
CCP2IF(1) 0000 0--0 0000 0--0
—
--00 0-0- --00 0-0-
SSP2IF ---- --00 ---- --00
015h
TMR0
Timer0 Module Register
xxxx xxxx uuuu uuuu
016h
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
017h
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
018h
T1CON
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
—
TMR1ON 0000 00-0 uuuu uu-u
019h
T1GCON
TMR1GE T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu
01Ah
TMR2
Timer2 Module Register
0000 0000 0000 0000
01Bh
PR2
Timer2 Period Register
1111 1111 1111 1111
01Ch T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
01Dh —
Unimplemented
—
—
01Eh
CPSCON0
CPSON
—
—
—
CPSRNG1 CPSRNG0 CPSOUT T0XCS 0--- 0000 0--- 0000
01Fh
CPSCON1
—
—
—
—
CPSCH3 CPSCH2 CPSCH1 CPSCH0 ---- 0000 ---- 0000
Legend:
Note 1:
2:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
PIC16F/LF1827 only.
These registers can be addressed from any bank.
DS41391C-page 30
Preliminary
2010 Microchip Technology Inc.
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