PIC16LF1826-I/SS View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LF1826-I/SS

18/20/28-Pin Flash Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC16F/LF1826/27

25.4.2 SYNCHRONOUS SLAVE MODE

The following bits are used to configure the EUSART

for Synchronous slave operation:

• SYNC = 1

• CSRC = 0

• SREN = 0 (for transmit); SREN = 1 (for receive)

• CREN = 0 (for transmit); CREN = 1 (for receive)

• SPEN = 1

Setting the SYNC bit of the TXSTA register configures the

device for synchronous operation. Clearing the CSRC bit

of the TXSTA register configures the device as a slave.

Clearing the SREN and CREN bits of the RCSTA register

ensures that the device is in the Transmit mode,

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

EUSART.

25.4.2.1 EUSART Synchronous Slave

Transmit

The operation of the Synchronous Master and Slave

modes are identical (see Section 25.4.1.3

“Synchronous Master Transmission”), except in the

case of the Sleep mode.

If two words are written to the TXREG and then the

SLEEP instruction is executed, the following will occur:

1. The first character will immediately transfer to

the TSR register and transmit.

2. The second word will remain in TXREG register.

3. The TXIF bit will not be set.

4. After the first character has been shifted out of

TSR, the TXREG register will transfer the second

character to the TSR and the TXIF bit will now be

set.

5. If the PEIE and TXIE bits are set, the interrupt

will wake the device from Sleep and execute the

next instruction. If the GIE bit is also set, the

program will call the Interrupt Service Routine.

25.4.2.2 Synchronous Slave Transmission

Set-up:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. Clear the ANSEL bit for the CK pin (if applicable).

3. Clear the CREN and SREN bits.

4. If interrupts are desired, set the TXIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

5. If 9-bit transmission is desired, set the TX9 bit.

6. Enable transmission by setting the TXEN bit.

7. If 9-bit transmission is selected, insert the Most

Significant bit into the TX9D bit.

8. Start transmission by writing the Least

Significant 8 bits to the TXREG register.

TABLE 25-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE

TRANSMISSION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register

on Page

APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL(1) CCP2SEL(1) P1DSEL P1CSEL CCP1SEL

122

APFCON1

—

—

—

—

—

—

—

TXCKSEL

122

BAUDCON ABDOVF RCIDL

—

SCKP

BRG16

—

WUE

ABDEN

298

INTCON

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

INTF

IOCIF

101

PIE1

TMR1GIE ADIE

RCIE

TXIE

SSPIE

CCP1IE TMR2IE TMR1IE

102

PIR1

TMR1GIF ADIF

RCIF

TXIF

SSPIF

CCP1IF TMR2IF TMR1IF

105

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

297

TRISB

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

129

TXREG

EUSART Transmit Data Register

289*

TXSTA

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

296

Legend:

*

Note 1:

— = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.

Page provides register information.

PIC16F/LF1827 only.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 313

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