PIC16F/LF1826/27
REGISTER 26-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1
U-0
—
bit 7
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
—
—
—
CPSCH3
CPSCH2
CPSCH1
R/W-0/0
CPSCH0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
CPSCH<3:0>: Capacitive Sensing Channel Select bits
If CPSON = 0:
These bits are ignored. No channel is selected.
If CPSON = 1:
0000 =
0001 =
0010 =
0011 =
0100 =
0101 =
0110 =
0111 =
1000 =
1001 =
1010 =
1011 =
1100 =
1101 =
1110 =
1111 =
channel 0, (CPS0)
channel 1, (CPS1)
channel 2, (CPS2)
channel 3, (CPS3)
channel 4, (CPS4)
channel 5, (CPS5)
channel 6, (CPS6)
channel 7, (CPS7)
channel 8, (CPS8)
channel 9, (CPS9)
channel 10, (CPS10)
channel 11, (CPS11)
Reserved. Do not use.
Reserved. Do not use.
Reserved. Do not use.
Reserved. Do not use.
TABLE 26-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
—
—
—
ANSA4 ANSA3 ANSA2 ANSA1 ANSA0
ANSELB
ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1
—
CPSCON0
CPSCON1
INTCON
CPSON
—
GIE
—
—
PEIE
—
—
TMR0IE
—
—
INTE
CPSRNG1 CPSRNG0
CPSCH3 CPSCH2
IOCIE TMR0IF
CPSOUT
CPSCH1
INTF
T0XCS
CPSCH0
IOCIF
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE
PSA
PS2
PS1
PS0
PIE1
TMR1GIE ADIE
RCIE
TXIE
SSP1IE CCP1IE TMR2IE TMR1IE
PIR1
TMR1GIF ADIF
RCIF
TXIF
SSP1IF CCP1IF TMR2IF TMR1IF
T1CON
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
—
TMR1ON
TxCON
—
TxOUTPS3 TxOUTPS2 TxOUTPS1 TxOUTPS0 TMRxON TxCKPS1 TxCKPS0
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the capacitive sensing module.
Register
on Page
125
130
320
321
91
177
92
96
187
193
124
129
2010 Microchip Technology Inc.
Preliminary
DS41391C-page 321