PIC16F1826-I View Datasheet(PDF) - Microchip Technology
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Description
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PIC16F1826-I Datasheet PDF : 406 Pages
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PIC16F/LF1826/27
8.5.4
PIE3 REGISTER(1)
The PIE3 register contains the interrupt enable bits, as
shown in Register 8-4.
Note 1: The PIE3 register is available only on the
PIC16F/LF1827 device.
2: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 8-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3(1)
U-0
—
bit 7
U-0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
—
CCP4IE
CCP3IE
TMR6IE
—
TMR4IE
U-0
—
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
CCP4IE: CCP4 Interrupt Enable bit
1 = Enables the CCP4 interrupt
0 = Disables the CCP4 interrupt
CCP3IE: CCP3 Interrupt Enable bit
1 = Enables the CCP3 interrupt
0 = Disables the CCP3 interrupt
TMR6IE: TMR6 to PR6 Match Interrupt Enable bit
1 = Enables the TMR6 to PR6 Match interrupt
0 = Disables the TMR6 to PR6 Match interrupt
Unimplemented: Read as ‘0’
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enables the TMR4 to PR4 Match interrupt
0 = Disables the TMR4 to PR4 Match interrupt
Unimplemented: Read as ‘0’
Note 1: This register is only available on PIC16F/LF1827.
DS41391C-page 94
Preliminary
2010 Microchip Technology Inc.
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