PIC18F4220-I View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F4220-I

28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

Microchip Technology

PIC18F4220-I Datasheet PDF : 388 Pages

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PIC18F2220/2320/4220/4320

EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

PROGRAM_MEMORY

BCF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

NOP

BSF

DECFSZ

GOTO

BCF

INTCON,GIE

55h

EECON2

AAh

EECON2

EECON1,WR

INTCON,GIE

COUNTER_HI

PROGRAM_LOOP

EECON1,WREN

; disable interrupts

; required sequence

; write 55H

; write AAH

; start program (CPU stall)

; re-enable interrupts

; loop until done

; disable write to memory

6.5.2 WRITE VERIFY

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in applications where excessive writes

can stress bits near the specification limit.

6.5.3

UNEXPECTED TERMINATION OF

WRITE OPERATION

If a write is terminated by an unplanned event, such as

loss of power or an unexpected Reset, the memory

location just programmed should be verified and repro-

grammed if needed. The WRERR bit is set when a

write operation is interrupted by a MCLR Reset, or a

WDT Time-out Reset, during normal operation. In

these situations, users can check the WRERR bit and

rewrite the location.

6.6 Flash Program Operation During

Code Protection

See Section 23.0 “Special Features of the CPU”

(Section 23.5 “Program Verification and Code Pro-

tection”) for details on code protection of Flash

program memory.

TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Name

Bit 7

Bit 6

Bit 5 Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Value on

all other

Resets

TBLPTRU

—

bit 21 Program Memory Table Pointer Upper Byte

(TBLPTR<20:16>)

TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)

TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)

TABLAT Program Memory Table Latch

INTCON GIE/GIEH PEIE/GIEL TMR0IE INTE RBIE TMR0IF INTF

RBIF

EECON2 EEPROM Control Register 2 (not a physical register)

EECON1 EEPGD CFGS

—

FREE WRERR WREN

IPR2

OSCFIP CMIP

—

EEIP BCLIP LVDIP TMR3IP CCP2IP

PIR2

OSCFIF CMIF

—

EEIF BCLIF LVDIF TMR3IF CCP2IF

PIE2

OSCFIE CMIE

—

EEIE BCLIE LVDIE TMR3IE CCP2IE

Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ‘0’.

Shaded cells are not used during Flash/EEPROM access.

--00 0000 --00 0000

0000 0000 0000 0000

0000 000x 0000 000u

—

xx-0 x000 uu-0 u000

11-1 1111 ---1 1111

00-0 0000 ---0 0000

 2003 Microchip Technology Inc.

DS39599C-page 79

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