STE2002(2002) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STE2002 Datasheet PDF : 51 Pages
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STE2002
If SCE stays low after the last bit of a command/data byte, the serial interface expects the MSB of the next byte
at the next SCLK positive edge.
A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all the internal
registers are cleared.
If SCE is low after the positive edge of RES, the serial interface is ready to receive data.
Throughout SOUT can be read only the driver I2C slave address. The Command sequence that allows to read
I2C slave address is reported in Fig. 34 & 35. SOUT is in High impedance in steady state and during data write.
It is possible to short circuit DOUT and SDIN and read I2C address without any additional lines.
Figure 32. Serial bus protocol - one byte transmission
SCE
D/C
SCLK
SDIN
MSB
Figure 33. Serial bus protocol - several byte transmission
LSB
D00IN1159
SCE
D/C
SCLK
SDIN
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
D00IN1160
Figure 34. Serial bus protocol - several byte transmission
SCE
D/C
SCLK
SDIN
SOUT
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
DB7
DB6
DB5
D00IN1160
High-Z
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
High-Z
Command Write
I2C Address Read
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