STM8S103xx, STM8S105xx
Pinouts and pin description
Table 5. Pin description for STM8S105 MCUs (continued)
Pin number
Input
Output
Pin name
Alternate
Default alternate function after
function
remap
[option bit]
39 35 - PE1/I2C_SCL
I/O X X X
O1 T(1) X Port E1 I2C clock
40 36 - PE0/CLK_CCO
I/O X X X
O3 X
X
Port E0
Configurable clock
output
41 37 25 PD0/TIM3_CC2
TIM1_BKIN
I/O X
X
X
HS O3 X
X
Port D0
Timer
3
-
channel
2
[AFR3]/
CLK_CCO
[AFR2]
42 38 26 PD1/SWIM
I/O X
X
X
HS O4 X
X
Port D1
SWIM data
interface
43 39 27 PD2/TIM3_CC1
I/O X
X
X
HS O3 X
X
Port D2
Timer
3
-
channel
1
TIM2_CC3
[AFR1]
44 40 28 PD3/TIM2_CC2
I/O X
X
X
HS O3 X
X
Port D3
Timer
2
-
channel
2
ADC_ETR
[AFR0]
45
41
29
PD4/TIM2_CC1/BEE
P
I/O
X
X
X
HS O3 X
X
Port D4
Timer
2
-
channel
1
BEEP output
[AFR7]
46 42 30 PD5/ LINUART_TX I/O X X X
O1 X
X
Port D5
LINUART data
transmit
47 43 31 PD6/ LINUART_RX I/O X X X
O1 X
X
Port D6
LINUART data
receive
48 44 32 PD7/TLI
I/O X X X
O1 X
X Port D7 Top level interrupt
TIM1_CC4
[AFR4]
1. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not
implemented)
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