STM8S105K6P6BTR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STM8S105K6P6BTR
STMicroelectronics
STM8S105K6P6BTR Datasheet PDF : 56 Pages
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STM8S103xx, STM8S105xx
6
Option bytes
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the address shown in
Table 7: Option bytes below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the
ROP and UBC options that can only be toggled in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM
communication protocol and debug module user manual (UM0470) for information on SWIM
programming procedures.
Table 7. Option bytes
Addr.
Option
name
Option
byte
no.
7
6
5
Option bits
4
3
2
1
Factory
default
0
setting
4800h Read-out
OPT0
ROP[7:0]
00h
protection
(ROP)
4801h User boot
OPT1
UBC[7:0]
00h
code(UBC)
4802h
NOPT1
NUBC[7:0]
FFh
4803h Alternate
OPT2
AFR7
AFR6
AFR5
AFR4
AFR3
AFR2
AFR1
AFR0
00h
function
4804h remapping
NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0
FFh
(AFR)
4805h Watchdog
option
OPT3
Reserved
LSI
IWDG
WWDG WWDG
00h
_EN
_HW
_HW
_HALT
4806h
NOPT3
Reserved
NLSI
NIWDG_ NWWDG NWWG
FFh
_EN
HW
_HW
_HALT
4807h Clock option
OPT4
Reserved
EXT
CKAWU
PRS
PRS
00h
CLK
SEL
C1
C0
4808h
NOPT4
Reserved
NEXT NCKAWUS NPR
NPR
FFh
CLK
EL
SC1
SC0
4809h HSE clock
OPT5
HSECNT[7:0]
00h
startup
480Ah
NOPT5
NHSECNT[7:0]
FFh
480Bh Reserved
OPT6
Reserved
00h
480Ch
NOPT6
Reserved
FFh
480Dh Flash wait
states
480Eh
OPT7
NOPT7
Reserved
Reserved
Wait state
00h
Nwait state FFh
487Eh Bootloader
OPTBL
BL[7:0]
00h
487Fh
NOPTBL
NBL[7:0]
FFh
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