Z8F041APJ020EG View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z8F041APJ020EG

High-Performance 8-Bit Microcontrollers Z8 Encore! XP® F082A Series

Zilog 

Z8 Encore! XP® F082A Series

Product Specification

91

Timer Reload High and Low Byte Registers

The Timer 0–1 Reload High and Low Byte (TxRH and TxRL) registers, shown in

Tables 54 and 55, store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the

Timer Reload High Byte Register are stored in a temporary holding register. When a write

to the Timer Reload Low Byte Register occurs, the temporary holding register value is

written to the Timer High Byte Register. This operation allows simultaneous updates of

the 16-bit Timer reload value.

In COMPARE Mode, the Timer Reload High and Low Byte registers store the 16-bit

Compare value.

Table 54. Timer 0–1 Reload High Byte Register (TxRH)

Bit

7

6

5

4

3

2

1

0

Field

TRH

RESET

1

1

1

1

1

1

1

1

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Address

F02H, F0AH

Table 55. Timer 0–1 Reload Low Byte Register (TxRL)

Bit

7

6

5

4

3

2

1

0

Field

TRL

RESET

1

1

1

1

1

1

1

1

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Address

F03H, F0BH

Bit

[7:0]

TRH, TRL

Description

Timer Reload Register High and Low

These two bytes form the 16-bit reload value, {TRH[7:0], TRL[7:0]}. This value sets the max-

imum count value which initiates a timer reload to 0001H. In COMPARE Mode, these two

bytes form the 16-bit Compare value.

PS022827-1212

PRELIMINARY

Timer Control Register Definitions

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