Z8F041APJ020EG View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z8F041APJ020EG

High-Performance 8-Bit Microcontrollers Z8 Encore! XP® F082A Series

Zilog 

Z8 Encore! XP® F082A Series

Product Specification

111

Bit

Field

RESET

R/W

Address

7

TEN

0

R/W

Table 63. UART Control 0 Register (U0CTL0)

6

REN

0

R/W

5

CTSE

0

R/W

4

3

PEN

PSEL

0

0

R/W

R/W

F42H

2

SBRK

0

R/W

1

STOP

0

R/W

0

LBEN

0

R/W

Bit

[7]

TEN

[6]

REN

[5]

CTSE

[4]

PEN

[3]

PSEL

[2]

SBRK

[1]

STOP

[0]

LBEN

Description

Transmit Enable

This bit enables or disables the transmitter. The enable is also controlled by the CTS signal

and the CTSE bit. If the CTS signal is Low and the CTSE bit is 1, the transmitter is enabled. 

0 = Transmitter disabled.

1 = Transmitter enabled.

Receive Enable

This bit enables or disables the receiver.

0 = Receiver disabled.

1 = Receiver enabled.

CTS Enable

0 = The CTS signal has no effect on the transmitter.

1 = The UART recognizes the CTS signal as an enable control from the transmitter.

Parity Enable

This bit enables or disables parity. Even or odd is determined by the PSEL bit.

0 = Parity is disabled.

1 = The transmitter sends data with an additional parity bit and the receiver receives an addi-

tional parity bit.

Parity Select

0 = Even parity is transmitted and expected on all received data. 

1 = Odd parity is transmitted and expected on all received data.

Send Break

This bit pauses or breaks data transmission. Sending a break interrupts any transmission in

progress, so ensure that the transmitter has finished sending data before setting this bit. 

0 = No break is sent.

1 = Forces a break condition by setting the output of the transmitter to zero.

Stop Bit Select

0 = The transmitter sends one stop bit.

1 = The transmitter sends two stop bits.

Loop Back Enable

0 = Normal operation.

1 = All transmitted data is looped back to the receiver.

PS022827-1212

PRELIMINARY

UART Control Register Definitions

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