Z8F041APJ020EG View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z8F041APJ020EG

High-Performance 8-Bit Microcontrollers Z8 Encore! XP® F082A Series

Zilog 

Z8 Encore! XP® F082A Series

Product Specification

192

Bit

[5]

DBGACK

[4:1]

[0]

RST

Description (Continued)

Debug Acknowledge

This bit enables the debug acknowledge feature. If this bit is set to 1, the OCD sends a

Debug Acknowledge character (FFH) to the host when a Breakpoint occurs.

0 = Debug Acknowledge is disabled.

1 = Debug Acknowledge is enabled.

Reserved

These bits are reserved and must be programmed to 0000.

Reset

Setting this bit to 1 resets the Z8F04xA family device. The device goes through a normal

Power-On Reset sequence with the exception that the On-Chip Debugger is not reset. This

bit is automatically cleared to 0 at the end of reset.

0 = No effect.

1 = Reset the Flash Read Protect Option Bit device.

OCD Status Register

The OCD Status Register reports status information about the current state of the debugger

and the system.

Table 111. OCD Status Register (OCDSTAT)

Bit

7

6

5

4

3

2

1

0

Field

DBG

HALT FRPENB

Reserved

RESET

0

0

0

0

0

0

0

0

R/W

R

R

R

R

R

R

R

R

Bit

Description

[7]

DBG

Debug Status

0 = NORMAL Mode.

1 = DEBUG Mode.

[6]

HALT

HALT Mode

0 = Not in HALT Mode.

1 = In HALT Mode.

[5]

Flash Read Protect Option Bit Enable

FRPENB 0 = FRP bit enabled, that allows disabling of many OCD commands.

1 = FRP bit has no effect.

[4:0]

Reserved

These bits are reserved and must be programmed to 00000.

PS022827-1212

PRELIMINARY

On-Chip Debugger Control Register

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