Z8 Encore! XPยฎ F082A Series
Product Specification
215
Table 128. eZ8 CPU Instruction Summary (Continued)
Assembly๏
Mnemonic
Symbolic Operation
Address
Mode
dst src
Opcode(s)
Flags
Fetch Instr.
Cycle Cycle
(Hex) C Z S V D H s
s
DA dst
dst ๏ฌ DA(dst)
R
40
* * *Xโโ 2
2
IR
41
2
3
DEC dst
dst ๏ฌ dst - 1
R
30
โ* * *โโ 2
2
IR
31
2
3
DECW dst
dst ๏ฌ dst - 1
RR
80
โ* * *โโ 2
5
IRR
81
2
6
DI
IRQCTL[7] ๏ฌ 0
8F
โโโโโโ 1
2
DJNZ dst, RA dst ๏ฌ dst โ 1๏
r
if dst ๏น 0๏
PC ๏ฌ PC + X
0A-FA โ โ โ โ โ โ 2
3
EI
IRQCTL[7] ๏ฌ 1
9F
โโโโโโ 1
2
HALT
Halt Mode
7F
โโโโโโ 1
2
INC dst
dst ๏ฌ dst + 1
R
20
โ* *โโโ 2
2
IR
21
2
3
r
0E-FE
1
2
INCW dst
dst ๏ฌ dst + 1
RR
A0
โ* * *โโ 2
5
IRR
A1
2
6
IRET
FLAGS ๏ฌ @SP๏
SP ๏ฌ SP + 1๏
PC ๏ฌ @SP๏
SP ๏ฌ SP + 2๏
IRQCTL[7] ๏ฌ 1
BF
****** 1
5
JP dst
PC ๏ฌ dst
DA
8D
โโโโโโ 3
2
IRR
C4
2
3
JP cc, dst
if cc is true๏
PC ๏ฌ dst
DA
0D-FD โ โ โ โ โ โ 3
2
Note: Flags Notation:
* = Value is a function of the result of the operation.๏
โ = Unaffected.๏
X = Undefined.
0 = Reset to 0.๏
1 = Set to 1.
PS022827-1212
PRELIMINARY
eZ8 CPU Instruction Summary